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1CY 7C34 2
This is an abbreviated datasheet. Contact a Cypress Representative for complete specifications. For new designs, please refer to the CY7C342B.
fax id: 6103
CY7C342
128-Macrocell MAX(R) EPLDs
Features
* * * * * 128 macrocells in 8 LABs 8 dedicated inputs, 52 bidirectional I/O pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology Available in 68-pin HLCC, PLCC, and PGA packages to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated. Externally, the CY7C342 provides eight dedicated inputs, one of which may be used as a system clock. There are 52 I/O pins that may be individually configured for input, output, or bidirectional data flow.
Functional Description
The CY7C342 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions. The 128 macrocells in the CY7C342 are divided into 8 Logic Array Blocks (LABs), 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C342 allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the functionality of 20-pin PLDs, the CY7C342 allows the replacement of over 50 TTL devices. By replacing large amounts of logic, the CY7C342 reduces board space, part count, and increases system reliability.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals that may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a signal pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
Timing Delays
Timing delays within the CY7C342 may be easily determined using Warp2(R), Warp2SimTM, or Warp3(R) software. The CY7C342 has fixed internal delays, allowing the user to determine the worst case timing delays for any design. For complete timing information the Warp3 software provides a timing simulator.
Logic Array Blocks
There are 8 logic array blocks in the CY7C342. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go
Selection Guide
7C342-25 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Military Industrial Maximum Static Current (mA) Commercial Military Industrial 25 250 320 320 225 275 275 7C342-30 30 250 320 320 225 275 275 7C342-35 35 250 320 320 225 275 275
MAX is a registered trademark of Altera Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor. Warp2Sim is a trademark of Cypress Semiconductor Corporation. Document #: 38-00500
Cypress Semiconductor Corporation
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3901 North First Street
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San Jose
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CA 95134
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408-943-2600 October 1995

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